Many power semiconductor devices are fabricated on the same semiconductor substrate. The devices are physically separated following processing via a so-called dicing process which can be accomplished by scribing and breaking the substrate, by mechanically sawing (e.g. with a dicing saw) or by laser cutting. In each case, the lateral edge of each device has crystal defects which result from the dicing process. Leakage current significantly increases due to the crystal defects if any equipotential lines are permitted to reach the lateral edge of the device, reducing the blocking voltage capacity of the device.
To ensure a sufficiently high blocking voltage capacity for high-voltage semiconductor devices fabricated from e.g. Si or SiC, suitable measures must be implemented in the edge termination region at the lateral edge of the device. For modern MOS (metal oxide semiconductor) controlled power switches such as SIPMOS transistors, IGBTs (insulated gate bipolar transistors) or DMOS (double-diffused metal-oxide-semiconductor) transistors as well as high-voltage diodes, the strength of the electric field must be fully dissipated between the active device region and the saw edge of the device. Otherwise, field magnification occurs at the edge of the device.
The higher the reverse capacity of the device, the more complicated are generally also the requirement on the passivation layers. For IGBT products, as well as the associated freewheeling diodes, reverse voltages of 600 V to up to 6.5 kV are currently required. The edge termination region is in this case frequently realized with a planar design. The purpose of the edge construction is to ensure that the equipotential lines are conducted from the inner part of the device to the surface in such a way that their curve and thickness do not lead to any premature onset of avalanche generation in the silicon, or to a dielectric breakdown in the passivation layers, and that the blocking capacity of the device will be lowered far below the value of the volume breakdown voltage.
Other critical locations are the steps and edges in the topology of the edge construction. Peak field strengths of several MV/cm can build up on the surface in these locations during dynamic operation, creating extremely high requirement for the robustness of the protective passivation layers on the surfaces. When these requirements are not fully met, there the device can fail after a certain number of switching cycles.
Several conventional techniques can be applied in order to ensure a sufficiently high blocking voltage capacity in the edge termination. Each of these techniques attempts to weaken the electric field on the surface and to increase the tolerance region relative to the surface charges. The intent is to create potential relationships on the surface of the semiconductor material which can be maintained in a stable manner over a long period of time. For mesa termination structures, the contouring of the edge of the semiconductor is performed in the form of inclined cross-sections or trenches created with the blocking pn-transitions. For planar termination structures, the dissipation of the field strength must be brought about with suitable masking techniques. Accordingly, either a lateral development of doping is provided with the doping concentration adjusted accordingly, or so-called field plate constructions are used, through which the strength of the surface field can be laterally dissipated in a suitable manner in the insulation layer surface which is located between the field plate constructions and the surface of the semiconductor.
However, a considerable portion of the surface of the device is required for the optimization of a highly blocking planar edge with respect to the blocking potential and blocking stability. Typically, a twofold or threefold base thickness is set for the width of the edge termination. The high area requirement arises because the curving of the equipotential lines occurs for the most part in the silicon so that they can be led out to the surface. The curving of the equipotential lines is connected with an increase of the electric field. If the field exceeds a critical value, an avalanche breakdown occurs. In order to keep the curve radius sufficiently low, a field plate construction with a cushion oxide for a 600 V device requires an edge termination width of approximately 200 to 250 μm. An edge width of more than 2,000 μm is required with such a structure already for a blocking capacity of 6.5 kV.
Also, a planar high-voltage termination edge increases the expense associated with optimizing the simulation and increases the process complexity during the manufacturing. An overly complex process is particularly expensive for high-voltage diodes because the basic structure in the active part of the device is relatively simple and only requires a few process steps.
In contrasts to planar edge termination structures, mesa edge termination structures shift (at least partially) the dissipation of the field strength in the vertical depth of the device and the edge requirement is thus correspondingly smaller. Such a mesa edge termination is widely used for the manufacturing of high-voltage devices in the long-established bipolar technology, such as for example for thyristors.
However, very rough, mechanical techniques such as grinding, lapping or sandblasting are employed, which cannot be integrated with the manufacturing of MOS devices for reasons related to defect density. Moreover, the devices must be isolated for mechanic edge processing (for example with laser cutting operations), and then further processed and finished as individual chips or dies. This is also not compatible with the manufacturing of wafers which have standard diameters at a high level of automation.
Alternative technologies which are compatible with MOS technology are now available with the development of modern trench cell concepts, for example with new IGBT generations, which are suitable for the manufacturing of a vertical edge termination. With the vertical design of the edge termination structure, a circumferential trench is formed at the device edge, approximately in the area of the kerf along the dies which are later separated, through the depth of the drift zone. The blocking voltage capacity is improved with the integration of the acceptors (p-type dopants) in the sidewall of the vertical trench. For alternative, the trench can be set off from the lateral edge of the device so that the terminating edge region serves as a lateral field plate which is connected to the rear side potential. The equipotential lines can thus be led to the upper part in the trench which is filled with a dielectric material, and the actual chip edge remains field-free.
With the implantation of a higher acceptor dose in the bottom of the trench as opposed to the sidewall, the depth of the trench can be reduced with a structure having a side field plate by about a half. The structure is thus suitable for process integration with thin wafer technology in which a highly doped carrier material is no longer used.
However, the reduction of trench depth together with an increasing so-called punch through (PT) dimensioning leads to a behaviour in which the equipotential lines running through the structure under the bottom of the trench are “curved back” with a relatively large curve radius in the outermost region to a channel stopper region. This requires a considerable amount of space for the width of the lateral field stop zone in order to prevent impacting of the space charge zone (SCZ) at the lateral saw edge, which leads to a massive leakage current increase due to the damage caused to the crystals. The width of the lateral field stop zone can correspond to twice the width of the edge trench depending on the strength of the PT dimensioning. This indeed holds strongly true without limitations only in the fast switching case, since under the conditions of a static blocking load, accumulation of holes occurs at the outer lateral trench edge due to thermal generation, which partially shield the field against lateral spread. However, numeric simulations provide evidence that the shielding effect practically disappears with a relatively small depth of the trench, such as for example a half of the thickness of the chip, and with increased PT dimensioning, and that hardly any effect is exerted on the distribution of the equipotential lines even in the static blocking mode.